>
>
>I am working with the Hiring Manager, so resumes will go directly to him.
>
>
>
>Can you think of any recent or past co-workers who might be interested?
>
>
>
>We sure appreciate your help!
>
>
>
>ASIC Verification Engineer
>
>12+ Month Contract
>
>Dallas, TX
>
>
>
>Necessary Skills:
>
>· ASIC verification expertise as a
>strong focus on your resume --- we are not
>looking for ASIC design engineers with some verification expertise.
>
>· Must have completed several complex
>Specman eVc/Specman or SystemVerilog test benches that are complex.
>
>· Must have knowledge of transactional
>verification processes – or --- OVM – or
>background in CPU or DSP type custom ASIC verification background.
>
>· Must have verification level background in either Verilog or VHDL
>
>· Must have strong scripting background
>using TCL, Perl, Python or similar scripting language
>
>
>
>Additional Skills:
>
>· Nice to have completed complex test
>bench with Verilog or VHDL and used Specman for test bench at block level.
>
>· Nice to have written ASIC tests in C
>or C++ for ASIC verification purposes.
>
>
>
>Thank you,
>
>
>
>Michael Barranco
>
>Formalized Design, Inc
>
>Colorado Springs, CO 80921
>
><mailto:michael.barranco_at_formalized.com>michael.barranco_at_formalized.com
>
>www.formalized.com
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Received on 2011-04-29 16:19:58